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CAT24M01
Table 4. PIN IMPEDANCE CHARACTERISTICS
V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C and V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unless otherwise speci ? ed.
Symbol
C IN (Note 5)
C IN (Note 5)
I WP , I A (Note 6)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current, Address Input Current (A 1 , A 2 )
Conditions
V IN = 0 V
V IN = 0 V
V IN < V IH , V CC = 5.5 V
Max
8
6
75
Units
pF
pF
m A
V IN < V IH , V CC = 3.3 V
V IN < V IH , V CC = 1.8 V
V IN > V IH
50
25
2
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
6. When not driven, the WP, A 1 , A 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull ? down is relatively
strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC ), the strong pull ? down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS (Note 7)
V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C and V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unless otherwise specified.
Standard
V CC = 1.8 V ? 5.5 V
Fast
V CC = 1.8 V ? 5.5 V
Fast ? Plus
V CC = 2.5 V ? 5.5 V
T A = ? 40 5 C to +85 5 C
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
F SCL
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R (Note 8)
t F (Note 8)
t SU:STO
t BUF
t AA
t DH
T i (Note 8)
t SU:WP
t HD:WP
t WR
t PU (Notes 8, 9)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between
STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL
and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
4
4.7
4
4.7
0
250
4
4.7
50
0
2.5
100
1,000
300
3.5
50
5
0.1
0.6
1.3
0.6
0.6
0
100
0.6
1.3
50
0
2.5
400
300
300
0.9
50
5
0.1
0.25
0.45
0.40
0.25
0
50
0.25
0.5
50
0
1
1,000
100
100
0.40
50
5
0.1
kHz
m s
m s
m s
m s
m s
ns
ns
ns
m s
m s
m s
ns
ns
m s
m s
ms
ms
7.
8.
9.
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t PU is the delay between the time V CC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITION S
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V CC to 0.8 x V CC
≤ 50 ns
0.3 x V CC , 0.7 x V CC
0.5 x V CC
Current Source: I L = 3 mA (V CC ≥ 2.5 V); I L = 1 mA (V CC < 2.5 V); C L = 100 pF
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